1. Field of the Invention
The present invention relates to a data synchronization apparatus. More particularly, the present invention relates to a data synchronization apparatus for relaying data.
2. Description of the Related Art
The problem of flow control is always present when a data producer transmits data to a data consumer. Take a digital audio application for example. A digital-to-analog converter (DAC) receives audio data from a data source for further processing. In this scenario, the data source is the producer and the DAC is the consumer. The data source transmits data using a universal serial bus (USB) interface, while the DAC receives data through an integrated interchip sound (I2S) interface. The problem is that the DAC cannot control the transmission rate of the data source, and ideally the receiving rate of the I2S interface should match the transmission rate of the USB interface. A conventional solution is using a phase-locked loop (PLL) to provide the clock signal of the I2S interface according to the transmission rate of the USB interface so that the receiving rate of the DAC matches the transmission rate of the data source.
However, this solution cannot solve every issue. Sometimes data are temporarily unavailable due to transmission loss or error. For the analog performance of the DAC, the data supply to the DAC should not be interrupted. In this case, the receiving rate of the DAC should not simply match with the transmission rate of the data source. The proper response is slowing down the receiving rate of the DAC until such a data underflow passes away. There is also the problem of data overflow. When the data source provides data faster than the DAC receives data, the receiving rate of the DAC has to increase accordingly. For an acceptable audio quality, the adjustment of the receiving rate must be gradual and steady. PLL alone cannot achieve these objectives. Therefore it is desirable to have an advanced solution for these issues.